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1 [Liou] [pdf] Evolution, Current Status and Future Trend of RF Transistors
2 [Jungemann] [pdf] Noise Analysis for a SiGe HBT by Hydrodynamic Device Simulation
3 [Weber] [pdf] Knowing the Key Factors in RF Power Amplifier Design
4 [Kuo] [pdf] Compact LDD/FD SOI CMOS Device Model Considering Energy Transport and Self Heating for SPICE Circuit Simulation
5 [Chew] [pdf] Impact of Deep N-well Implantation on Substrate Noise Coupling and RF Transistor Performance for Systems-on-a-Chip Integration
6 [Kotov] [pdf] Tunneling Phenomenon in SuperFlash Cell
7 [Shimizu] [pdf] Design Sensitivity in Quasi-One-Dimensional Silicon-Based Photonic Crystalline Waveguides
8 [Chen] [pdf] Failure Characterization of ESD Damage in Low Temperature Poly-Si TFTs
9 [Nakajima] [pdf] Off-Leakage and Drive Current Characteristics of Sub-100-nm SOI MOSFETs and Impact of Quantum Tunnel Current
10 [Zimmermann] [pdf] Fast CMOS-Integrated Finger Photodiodes for a Wide Spectral Range
11 [Tsuchiya] [pdf] Evaluation of Interface Trap Density in a SiGe/Si Heterostructure Using a Charge Pumping Technique and Correlation between the Trap Density and Low Frequency Noise in SiGe-Channel pMOSFETs
12 [Kuo2] [pdf] Compact Breakdown Model for PD SOI NMOS Devices Considering BJT/MOS Impact Ionization for SPICE Circuit Simulation
13 [Prgaldiny] [pdf] A New Physical Modeling of Parasitic Capacitances of Deep-Submicron LDD MOSFETs
14 [Soree2] [pdf] Dissipative transport in quantum wires
15 [Sadovnikov] [pdf] Influence of the Extrinsic Base on the Base Current Kink in SiGe BJTs
16 [Bechtold2] [pdf] Automatic Order Reduction of Thermo-Electric Models for MEMS: Arnoldi versus Guyan
17 [Rengel] [pdf] Static and RF behaviour of short-gate Fully-Depleted Silicon-on-Insulator MOSFETs: numerical and experimental analysis
18 [Hakim3] [pdf] Small Signal Characterization of Thin Film Single Halo SOI MOSFET For Mixed Mode Analog and Digital Applications
19 [Rubaldo] [pdf] Hot carrier reliability improvement of PMOS I/O's transistor in advanced CMOS technology
20 [Cacciato] [pdf] Reduction of Bitline to Control Gate leakage for improved embedded 0.18 um FLASH Yield and Reliability
21 [Choi] [pdf] Reverse-Order Source/Drain (R-S/D) Combined with LDD Offset Spacer and Its Application to 50nm Physical-Gate-Length nMOSFETs
22 [Joseph] [pdf] Comments on Existing 1/f Noise Models:Spice, HSPICE and BSIM3v3 for MOSFETs in Circuit Simulators
23 [Schambach] [pdf] Micromachined Mercury Sensor
24 [Lugstein] [pdf] Post-Process CMOS Front End Engineering With Focused Ion Beams
25 [MonzioCompagnoni] [pdf] Degradation Dynamics for Deep Scaled p-MOSFET's during Hot-Carrier Stress
26 [Hehemann] [pdf] A CMOS Photodiode Array with Linearized Spectral Response and Spatially Distributed Light Intensity Detection for the Use in Optical Storage Systems
27 [pascal] [pdf] Nano crystal memory devices characterization using the charge pumping technique
28 [Pichler] [pdf] Properties of Vacancies in Silicon Determined from Laser--Annealing Experiments
29 [Toita] [pdf] Gate and Drain Bias Dependences of 1/f Noise Amplitude in MOSFETs in the Linear and Saturation Regions
30 [Lander] [pdf] A Tuneable Metal Gate Work Function Using Solid State Diffusion of Nitrogen
31 [Roccaforte] [pdf] High reproducible ideal SiC Schottky rectifiers by controlling surface preparation and thermal treatments
32 [SansigoloLujan] [pdf] Impact of ALCVD and PVD Titanium Nitride Deposition on Metal Gate Capacitors
33 [Elattari] [pdf] Self-Consistent Solution of the Schrodinger and Poisson Equations for Accumulated MOS Capacitors with Ultra-thin Layers
34 [Bauza4] [pdf] Extraction of Si-SiO2 interface trap densities in MOSFET's with oxides down to 1.3 nm thick
35 [Roncaglia] [pdf] Modeling of Large-Area nMOS Devices for Smart-Power Applications
No paper 36
37 [Mahapatra] [pdf] Performance and reliability of high density flash EEPROMs under CHISEL programming operation
38 [Gnani] [pdf] Extraction method for the impact-ionization multiplication factor in silicon at large operating temperatures
No paper 39
40 [Kwon] [pdf] Improved Isolated RESURF Technology for a Multi Power BCD Process
41 [Chen3] [pdf] Threshold Variations for Undoped Double-Gate MOSFET's
42 [Sadovnikov2] [pdf] Effects of Boron and Germanium Base Profiles on SiGe and SiGe:C BJT Characteristics
43 [Dosev] [pdf] Simulation and Modeling of Nanocrystalline Silicon Thin Film Transistors
44 [Coppens] [pdf] Ar Sputter Etch to Improve the Insulator Quality in Metal Capacitors
45 [Aresu] [pdf] SILC Measurements of Thin SiO2 at Low Voltages: High-resolution measurements and interpretation
46 [Matsumoto] [pdf] Design Guidelines for Linear Amplification and Low-insertion loss in 5-GHz-band SOI Power MOSFETs
47 [Ghetti] [pdf] Coupled Monte Carlo Simulation of Si and SiO2 Transport in MOS Transistors
48 [Kerner] [pdf] Metal Rings as Quantum Bits
49 [Peng] [pdf] An Ultra-Thin Polycrystalline-Silicon Thin-Film Transistor with SiGe Raised Source/Drain
50 [Henson] [pdf] Investigation of performance improvement and gate-to-junction leakage reduction for the 90nm CMOS gate stack architecture
51 [Fatkhoutdinov2] [pdf] Impact of Post Metal Etch Resist Strip in Plasma on Plasma Charge-Induced Erosion of Tungsten-Plugs
52 [Reisch] [pdf] High-Frequency Bipolar Transistor Noise Modeling
53 [Moens] [pdf] Future Trends in Intelligent Interface Technologies for 42V Battery Automotive Applications
54 [Kwon2] [pdf] Suppression of CoSix Induced Leakage Current using Novel Capping Process for Sub-0.10um node SRAM Cell technology
55 [Lukyanchikova] [pdf] On the origin of the 1/f1.7 noise in deep submicron partially depleted SOI transistors
56 [Ielmini] [pdf] Monitoring Flash EEPROM Reliability by Equivalent Cell Analysis
57 [LEE] [pdf] Fabrication of 0.1-um pMOSFETs with SiGe-Channel and Elevated B-Doped SiGe Source and Drain Layers
No paper 58
59 [WC3] [pdf] Temperature-Dependent Characteristics of an n+-InGaAs/n-GaAs Composite Doped Channel (CDC) Heterostructure Field-Effect Transistor
60 [Rhayem] [pdf] Impact of Scaling Down from 0.25um to 0.18um CMOS Technology on 1/f Noise: Characterisation and Modelling
61 [WC4] [pdf] On the n+-GaAs/p+-InGaP/n--GaAs High-Barrier Camel-Like Gate Transistor for High-Breakdown, Low-Leakage and High-Temperature Operations
62 [Rucker3] [pdf] Antimony as Substitute for Arsenic to Eliminate Enhanced Diffusion Effects
63 [HM] [pdf] An InGaP/GaAs Resonant-Tunnelling Bipolar Transistor (RTBT) with Multiple Negative-Differential-Resistance (MNDR) Phenomena
64 [KB] [pdf] Characteristics of Polysilicon Resistors for Sub-Quarter Micron CMOS Applications
65 [Dimitri] [pdf] Clamped-Clamped Beam Micro-Mechanical Resonators in Thick-Film Epitaxial Polysilicon Technology
66 [Zhang] [pdf] A Viable Self-aligned Bottom-Gate MOSFET Technology for High Density and Low Voltage SRAM
67 [Chimenton] [pdf] Impact of Tunnel Oxide Thickness on Erratic Erase in Flash Memories
68 [Abdelkarim] [pdf] Inversion Layer Quantization Impact on the Interpretation of 1/f Noise in Deep Submicron CMOS Transistors
69 [Jankovic2] [pdf] Variable-Gain Inversion Layer Emitter Phototransistor in CMOS Technology
70 [Caputo] [pdf] Effect of Pulsed Stress on Leakage Current In MOS Capacitors For Non-Volatile Memory Applications
71 [deCesare] [pdf] LOW PINCH-OFF VOLTAGE AMORPHOUS SILICON JUNCTION FIELD-EFFECT TRANSISTOR: SIMULATION AND EXPERIMENT
72 [Sakalas] [pdf] Microwave noise Modeling of the 0.18um Gate Length Mosfets with a 60GHz cut-off frequency
73 [Kunz] [pdf] Reduction of parasitic capacitance in vertical MOSFET's by fillet local oxidation (FILOX)
74 [Ragi] [pdf] Modeling the C-V Characteristics of Heterodimensional Schottky Contacts
75 [Kunz4] [pdf] Application of Polycrystalline SiGe for Gain Control in SiGe Heterojunction Bipolar Transistors
76 [Malik] [pdf] Photoelectric and Tensometric Properties of a Metal Phthalocyanine-Silicon Junctions
77 [Sorge] [pdf] Implantation Dose Profiling by MOS C-V Measurements
78 [Baek2] [pdf] Characteristics of HfO2 pMOSFET with ultrashallow junction prepared by plasma doping and laser annealing
79 [Wang] [pdf] Compact Quantum Mechanical Device Models for MOSFETs in Gigascale Integration(GSI)
80 [Gehring2] [pdf] Transmission Coefficient Estimation for High-K Gate Stack Evaluation
81 [Cowern] [pdf] Diffusion Suppression in Silicon by Substitutional C Doping
82 [Stojcevski] [pdf] Low Power, 3-bit CMOS Pipeline ADC with Reduced Complexity Flash Architecture
83 [Ryzhii] [pdf] Device Model of Integrated QWIP-HBT-LED Pixel for Infrared Focal Plane Arrays
84 [Poyai] [pdf] Impact of p-Well Implantation Parameters on Junction Leakage
85 [Paschen] [pdf] High Temperature CMOS Process with Dielectric Isolation
86 [Dubois] [pdf] Impact of source/drain implants on threshold voltage matching in deep sub-micron CMOS technologies
87 [Fix] [pdf] Fast polymer integrated circuits based on a polyfluorene derivative
88 [Lee2] [pdf] Highly Extendible Memory Cell Architecture for Reliable Data Retention Time for 0.10mm Technology Node and beyond
89 [Rantzer] [pdf] Deep Trap Modelling and Transient Measurements of a-Si:H p-i-n Diodes
90 [Bagnoli] [pdf] Study of Hot-spot Phenomena in Cellular Power Transistors by Analytical Electro-Thermal Simulation
91 [Alessandria] [pdf] Integrated Si-based Opto-Couplers: a Novel Approach to Galvanic Isolation
92 [Brezeanu3] [pdf] Numerical and Analytical Study of 6H-SiC Detectors with High UV Performance
No paper 93
94 [Gloesekoetter] [pdf] Pseudo Dynamic Gate Design based on the Resonant Tunneling-Bipolar Transistor (RTBT)
95 [Frere] [pdf] A New Improved Model for LDMOS Transistors under Different Gate and Drain Bias Conditions
96 [Horstmann] [pdf] Lithography Independent Fabrication of Nano-MOS-Transistors with W = 25 nm and L = 25 nm
97 [Donaghy] [pdf] Investigating 50nm channel length vertical MOSFET containing a dielectric pocket, in a circuit environment
98 [Pogany] [pdf] A method for extraction of power dissipating sources from interferometric thermal mapping measurements
99 [Bakeroot] [pdf] Cost Effective Implementation of a 90 V RESURF P-type Drain Extended MOS in a 0.35 um Based Smart Power Technology
100 [Liu] [pdf] Characteristics of Sub-100nm High-k Gate Dielectrics MOSFETs With Different Source/Drain Structure
101 [Kikuchi2] [pdf] Stability of High-k Thin Films for Wet Process
102 [Heiskanen] [pdf] Implementing Self-Heating Effects into a Volterra Simulator
103 [Arshak] [pdf] Thick Film Gamma Radiation Sensors with Sensitive Layers of NiO and La2O3–Fe2O3 Mixture
104 [RJohannes] [pdf] Scaling considerations for fully-depleted SOI transistors down to the 20nm gate length regime
105 [Akama] [pdf] Stability of High-k Thin Films in Moisture Ambience - The Effect of Dissolution Gas from Acryl Apparatus -
106 [Yamamoto] [pdf] Electrical Characteristics Improvement of Dy2O3 Thin Films by In-situ Vacuum Anneal
107 [Ackaert2] [pdf] Use of Oxynitride Dielectric to Maximise the Growth Rate of Selective Epitaxial Base Layer in a Self-Aligned Double-Polysilicon SiGe Bipolar Transistors
108 [Taguchi] [pdf] Annealing Condition Dependence of Electrical Characteristics.
109 [Vandenbosch] [pdf] Identification of Critical Parameters for Plasma Process-Induced Damage in 130 and 100 nm CMOS Technologies
110 [Hofmann] [pdf] Passive DNA Sensor with Gold Electrodes Fabricated in a CMOS Backend Process
111 [Ohshima] [pdf] Electrical Characteristics of Gd2O3 thin film deposited on Si substrate.
112 [Rosmeulen2] [pdf] Electrical Characterisation of Silicon-Rich-Oxide Based Memory Cells Using Pulsed Current-Voltage Techniques
113 [Kashiwagi] [pdf] Characteristics of High-k Gd2O3 Films Deposited on Different Orientation of Si Substrate
114 [LeRoyer] [pdf] Accurate modeling of Quantum-Dot based Multi Tunnel Junction Memory: Optimization and process dispersions analyzes for DRAM applications
115 [Schenkel] [pdf] TCAD Based Design Methodology for Substrate Current Control in Smart Power ICs
116 [Khlyap] [pdf] Numerical simulation of parameters of ZnCdHgTe films and
117 [Scheinert] [pdf] Simulated influence of bulk traps on the subthreshold characteristics of an organic field effect transistor
118 [Brederlow] [pdf] Investigation of the Thermal Noise of MOS Transistors under
119 [Oulmane] [pdf] Accurate Delay Metric for On-chip Resistive Interconnect
120 [Hisamitsu] [pdf] Temperature-Independence-Point Properties for 0.1um-scale Pocket-Implant Technologies and the Impact on Circuits Design
121 [Dieudonn] [pdf] Low frequency noise in 0.12 �m Partially and Fully Depleted SOI technology
122 [Wilson] [pdf] A 12Volt, 12GHz Complementary Bipolar Technology for High Frequency Analogue Applications
123 [RichardsJr] [pdf] Comparison of the Gate Tunneling Current in Ultrathin-Oxide Inversion and Accumulation MOSFETs
124 [Vermandel] [pdf] Optimising High-Voltage Devices in a Smart Power Technology, using the RESurF-effect and TCAD.
125 [DellaCorte] [pdf] Design and simulation of an a-Si:H/GaAs heterojunction bipolar transistor
126 [Cubaynes] [pdf] Gate dielectrics for high performance and low power CMOS SoC applications
127 [Grgec] [pdf] Efficient Monte Carlo Simulation of Tunnel Currents in MOS Structures
128 [Nguyen] [pdf] Improved Modified Local Density Approximation for the Modeling of Size Quantization in pMOSFETs
129 [Maget] [pdf] Voltage-controlled substrate structure for integrated inductors in standard digital CMOS technologies
130 [Huang] [pdf] Temperature Effects of Low Noise InGaP/InGaAs/GaAs PHEMTs
131 [LeMinh] [pdf] Monolithic Integration of a Novel Microfluidic Device with Silicon Light Emitting Diode-Antifuse and Photodetector
132 [Mahapatra2] [pdf] Quasi-analytical modelling of drain current and conductance of Single Electron Transistors with MIB
133 [Pascal] [pdf] Gate Material Properties Induced 0.25�m SRAM Marginality
134 [Croon] [pdf] Influence of Doping Profile and Halo Implantation on the Threshold Voltage Mismatch of a 0.13um CMOS Technology
135 [Fraboulet] [pdf] Coulomb Blockade in Thin SOI Nanodevices
136 [Brown] [pdf] Mixing Sources of Intrinsic Parameter Fluctuations in the Simulation of Sub-100nm MOSFETs
137 [Straube] [pdf] SiGe pMOSFETs Fabricated on Novel SiGe Virtual Substrates Grown on 10�m x 10�m Pillars.
138 [Aarts] [pdf] A Robust and Physically Based Compact SOI-LDMOS Model
139 [Castagna] [pdf] Quantum Dot Materials and Devices for Light Emission in Silicon
140 [Wu] [pdf] Improved Compact RF-Noise Modelling for Deep Sub-Micron MOSFETs
141 [Vieregge] [pdf] Reducing the Threshold Voltage Deviation for sub-100nm Transistors using Midbandgap-Gatematerials
No paper 142
143 [Reggiani] [pdf] Electron Transport in Semiconductor-Insulator Structures Using the Full-Band Dispersion Relation of Si and SiO2
No paper 144
145 [JOSSE] [pdf] Spike anneal optimization for digital and analogue high performance 0.13 �m CMOS platform
146 [Morillon] [pdf] Realization of a SCR on an Epitaxial Substrate Using Al Thermomigration
147 [REYTAURIAC2] [pdf] Process and device simulation of power VDMOS transistors in Bipolar/CMOS/DMOS technology
148 [Laurent] [pdf] Engineering of 80V Vertical n-DMOS in a 0.35um CMOS Technology
149 [Kalna] [pdf] Tunnelling and impact ionization in scaled double doped PHEMTs
150 [mariucci] [pdf] Mechanisms of dopant redistribution and retention in Silicon following ultra-low energy Boron implantation and excimer laser annealing
151 [ANGHEL] [pdf] Universal Test Structure and Characterization Method for Bias-Dependent Drift Series Resistance of HV MOSFETs
152 [Daliento] [pdf] A New Test Structure for In-situ Measurements of interface Recombination During Surface Treatments
153 [Sturm] [pdf] Integrated Photodiodes in Standard BiCMOS Technology
154 [schwantes] [pdf] impact of statistical threshold voltage fluctuation and quantum mechanical effects on cmos circuits with gigabit feature size
155 [Schulz] [pdf] Impact of technology parameters on inverter-delay of UTB-SOI CMOS
156 [Kundu] [pdf] Electron Transit Time Enhancement In Photodetectors For High Speed Imaging
No paper 157
158 [schwantes2] [pdf] impact of stochastic dopant variation and the copper size effect on gigascale integration
159 [Cola] [pdf] Photodetector with Internal Aiding Field Based-on GaAs/AlGaAs Heterostructures
160 [Schwalke] [pdf] Process Integration of Crystalline Pr2O3 High-k Gate Dielectrics
161 [Zan] [pdf] Novel small-dimension poly-Si TFTs with improved driving current and suppressed short channel effects
162 [Wang2] [pdf] Accurate Modelling of Thin-Film Resistor up to 40 GHz
163 [Das] [pdf] Effect of annealing on wet oxidation of AlxGa1-xAs Layer
164 [Olsen] [pdf] Si/SiGe Cross-hatching: a Good Indicator of Strained Si MOSFET Performance
165 [Li] [pdf] Ultra-Thin Oxide Lifetime Estimation Using Transistor Degradation
166 [Axelrad] [pdf] Efficient Analysis and Optimization of ESD Protection Circuits
167 [Mahapatra3] [pdf] Substrate bias effect on cycling induced performance degradation of Flash EEPROMs
168 [Dixit] [pdf] A Novel Dynamic Threshold Operation Using the Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime
169 [Basset] [pdf] Design of a Remote Control System for a Wireless Microrobot
170 [Malik2] [pdf] Optoelectronics properties of FTO/SRO/Si radiation sensors
171 [Kim2] [pdf] The Advanced RESURF Structure to improve On-Resistance in BCDMOS
172 [Tartagni] [pdf] A Comparative Analysis of Active and Passive Pixel CMOS Image Sensors
173 [Specht] [pdf] Simulation of high-K tunnel barriers for nonvolatile floating gate memories
174 [Nguyen2] [pdf] Through-Wafer Copper Electroplating for RF Silicon Technology
175 [Amakawa] [pdf] A new approach to failure analysis and yield enhancement of very large-scale integrated systems
176 [IcazaDeckelmann] [pdf] UIS-Failure of DMOS Power Transistors
177 [Kang2] [pdf] Fabrication and Experimental Results of Lateral Trench Electrode IGBT
178 [Jurczak] [pdf] Elevated Co-Silicide for sub-100nm High Performance and RF CMOS
179 [Ingrosso] [pdf] Monte Carlo Simulation of Program and Erase Charge Distributions in NROM(TM) Devices
180 [Tavel] [pdf] Investigations on Poly-SiGe gate in full 0.1�m CMOS integration
181 [Kolhatkar] [pdf] Constant and Switched Bias Low Frequency Noise in p-MOSFETs with Varying Gate Oxide Thickness
182 [Avellan] [pdf] Temperature dependence of the hard breakdown current of MOS capacitors
183 [Barraud] [pdf] Effects of random discrete impurities in ultra-short MOSFET using 3D Monte Carlo simulation
184 [Moroz] [pdf] Exploring Methods for Adequate Simulation of Sub-100nm Devices
185 [Gopinath2] [pdf] Effects of Stress-Induced Bandgap Narrowing on Reverse-Bias Junction Behavior
186 [Gopinath] [pdf] A Simple and Accurate HSPICE Compatible Gate Leakage Macro Model
187 [Kim3] [pdf] A Low On-Resistance 700V Charge Balanced LDMOS with Intersected WELL Structure.
No paper 188
189 [Kim4] [pdf] A New Latch-Up Free Complementary Bipolar Process using PBSOI Technique
190 [TorresTorres2] [pdf] A New S-parameter Measurement-Based Method for MOSFET Gate Resistance Extraction
191 [Kim5] [pdf] High performance 0.1um CMOS device with suppressed parasitic junction capacitance and junction leakage current
192 [Singh] [pdf] Scaling Behaviour of Large-grain Polysilicon MOSFETs
193 [jeremy] [pdf] New mechanism of body charging in partially depleted SOI-MOSFETs with ultra-thin gate oxides
194 [Arnaud] [pdf] Channel architecture optimisation to reduce RNCE of deep sub-micron devices
195 [Arnaud2] [pdf] Gate oxide process impact on RNCE for advanced CMOS transistors
196 [Obreja2] [pdf] On the High Temperature Operation of High Voltage Power Devices
197 [Park] [pdf] Lateral Trench Gate Super-Junction SOI-LDMOSFETs with Low On-Resistance
198 [RodrguezTorres] [pdf] Three-Dimensional Analysis of a MAGFET at 300 K and 77 K
199 [Kilchytska] [pdf] Substrate Effects on the Small-Signal Characteristics of SOI MOSFETs
200 [Lienemann] [pdf] Volume shrinking in Micro-Fluidic Self-Assembly
201 [Collaert] [pdf] Influence of the Ge-concentration and RTA on the device performance of strained Si/SiGe pMOS devices
202 [Garzella] [pdf] LaNixFe1-xO3 thin films: p-type ethanol sensors
203 [Georges] [pdf] Channel Engineering Study for 50 nm P-Channel MOSFET
204 [David] [pdf] Raised Source/Drain on 50nm CMOS Circuits : Propagation Delay and Dynamic Power Optimizations
205 [Cristoloveanu] [pdf] The Four-Gate Transistor
206 [Jain] [pdf] A novel, low-power Capacitive waveform transformer
207 [Natali] [pdf] Hybrid metal-organic photodetectors based on a new class of metal-dithiolenes
208 [Esseni2] [pdf] An Improved Model for Electron Mobility Degradation by Remote Coulomb Scattering in Ultra-Thin Oxide MOSFETs
209 [Heitzinger] [pdf] An Algorithm for Smoothing Three-Dimensional Monte Carlo Ion Implantation Simulation Results
210 [PERRIN] [pdf] A Complete Evaluation of Trench Oxide Thickness Effect on Advanced ULSI
211 [Hsiung] [pdf] 50nm Schottky Barrier CMOS with Conventional Silicide
212 [XUE] [pdf] Array-Based Electrical Detector of Integrated DNA Identification System for Genetic Chip Applications
213 [Lundgren] [pdf] A MOS Nanogap Device Structure for Characterisation of Nano-scale Objects
214 [Gruhle] [pdf] The Double-Bandgap-Narrowing Transistor
215 [Kaczer] [pdf] Understanding nMOSFET characteristics after soft breakdown and their dependence on the breakdown location
216 [Aderstedt] [pdf] A Compact Model of the MOS Tunnel Emitter Transistor
217 [Sareen] [pdf] Effect of Si Cap Layer Thickness on Parasitic Channel Operation in SiSiGe MOS Structures
218 [Pejnefors] [pdf] A Self-Aligned Double Poly-Si Process Utilizing Non-Selective Epitaxy of SiGe:C for Intrinsic Base and Poly-SiGe for Extrinsic Base
219 [Kang4] [pdf] The characteristics of leakage current mechanisms and SILC effects of Al2O3 gate dielectric
220 [Rantzer2] [pdf] Bulk Wafer Defects Observable in Vision Chips
221 [Carrre] [pdf] Triple Gate Oxide by Nitrogen Implantation Integrated in a 0.13�m CMOS Flow
222 [Jackson] [pdf] Towards an Integrated Bulk/SOI Active Pixel APD Sensor: Bulk Substrate Inspection with Geiger Mode Avalanche Photodiodes
223 [Cuoco] [pdf] Experimental Verification of the Smoothie Database Model for Third and Fifth Order Intermodulation Distortion
224 [MARCON] [pdf] Determination of beryllium and self-interstitial parameters for modeling of Be activation implanted in InGaAs
225 [Coli] [pdf] Influence of dot size and density on the program characteristics of nanocrystal Flash memories
226 [MOUIS] [pdf] Electron Transport in Nanoscale Double-Gate MOSFETs from Monte-Carlo and Quantum Ballistic Simulation
227 [Lindgren] [pdf] Enhanced intrinsic gain (gm/gd) of PMOSFETs with a Si(0.7)Ge(0.3) channel
228 [Mller] [pdf] Advanced Junction Engineering for 60nm-CMOS Transistors
229 [Garros] [pdf] Investigation of HfO2 dielectric stacks deposited by ALD with a mercury probe
230 [Otn] [pdf] Modeling of Accumulation MOS Capacitors
231 [vonHaartman] [pdf] An experimental study of the influence of channel positioning on low-frequency noise in Si(0.7)Ge(0.3) pMOSFETs
232 [Burenkov] [pdf] Three-dimensional simulation of the channel stop implant effects in sub-quarter micron PMOS transistors
233 [Gwoziecki] [pdf] Physics of the subthreshold slope - initial improvement and final degradation in short CMOS devices
234 [Lombardo] [pdf] Programming by Tunneling in Nanocrystal Memories
235 [Nenadovic] [pdf] High-performance Silicon-On-Glass VDMOS transistor for RF-power applications
236 [Heitzinger2] [pdf] On Increasing the Accuracy of Simulations of Deposition and Etching Processes Using Radiosity and the Level Set Method
237 [Frederic2] [pdf] Gate length scaling in high fMAX Si/SiGe n-MODFET
238 [Bidaud] [pdf] Thermal Nitridation of Chemical Dielectrics as an Easy Approach to Ultra-thin Gate Oxide Processing
239 [Tsai] [pdf] Direct-Current Performance Improvements of Al0.45Ga0.55As/GaAs Digital Graded Superlattice-Emitter Heterojunction Bipolar Transistors by Wet-Oxidation
240 [CONTARET2] [pdf] Conduction and Noise Modelling of Submicronic Devices: Comparison Between ISE-TCAD Software and Microscopic Simulations
241 [Venezia] [pdf] The RF potential of high-performance 100nm CMOS technology
242 [Tan2] [pdf] Reduction of Short-Channel Effects and Improvement in Microwave Characteristics for V-groove Gate Pseudomorphic Doped-Channel HFET with Dual V-groove Gate Structure
243 [Ankarcrona] [pdf] A Novel General Direct Extraction Technique Used For a RF MOSFET Small-Signal Equivalent Circuit
244 [vanderWel] [pdf] Measurement of MOSFET LF Noise Under Large Signal RF Excitation
245 [Lartigau] [pdf] Comparative study of 1/f noise in bulk and SOI MOS devices
246 [Koricic2] [pdf] Investigation of the Extrinsic Base Effect on High Frequency Performance of SOI Lateral Bipolar Transistors (LBT)
247 [Augendre] [pdf] Controlling STI-related parasitic conduction in 90 nm CMOS and below
248 [Stellari2] [pdf] CMOS circuit analysis with luminescence measurements and simulations
249 [JOHANSSON] [pdf] ZrO2 gate dielectrics prepared by e-beam deposition of Zr and YSZ films and post annealing processes
250 [Jha2] [pdf] Optimization of Single Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliability
251 [ABBOUN] [pdf] Self Heating in InP DHBT Technology for 40 Gb/s ICs
252 [Austin] [pdf] Unified 2D Short Channel Effects Model for Bulk CMOS FETs
253 [Clerc] [pdf] Investigation on Convergence and Stability of Self-Consistent Monte Carlo Device Simulations
254 [Giudice] [pdf] A CMOS Compatible Single-Photon Avalanche Diode
255 [Maxim] [pdf] Physically-Based Matching Model for Deep-submicron MOS Transistors
256 [Gerardi] [pdf] Reliability and Retention Study of Nanocrystal Cell Array
257 [Heinle] [pdf] Vertical high voltage devices on thick SOI with back-end trench formation
258 [Fiori] [pdf] Modeling of ballistic nanoscale MOSFETs
259 [Mirabedini] [pdf] 65 nm Transistors for a 90 nm CMOS SOC Platform
260 [Guiducci] [pdf] A Biosensor for Direct Detection of DNA Sequences Based on Capacitance Measurements
261 [Suligoj] [pdf] A New Compact Horizontal Current Bipolar Transistor (HCBT) Fabricated in (110) Wafers
262 [McCarthy] [pdf] A Novel CMOS Compatible Top-Floating-Gate Flash EEPROM Cell.
263 [Froment] [pdf] Improvement in the prediction of Boron diffusion during a Spike Annealing for Ultra-Shallow Junctions
264 [Furuta] [pdf] Tunnel Barrier Properties of Polycrystalline-Si Single-Electron Transistor
265 [Fobelets] [pdf] Experimental study of depletion mode Si/SiGe MOSFETs for low-temperature operation
266 [Staedele] [pdf] Influence of source-drain tunneling on the subthreshold behavior of sub-10nm double-gate MOSFETs
267 [Bourenkov] [pdf] Benchmarking of Table Methods for MOSFET modelling
268 [Redolfi] [pdf] Improved Deep Sub-micron CMOS Ring Oscillator Performance with n-HDD and n-LDD P+ + As+ Co-Implant
269 [Veloso2] [pdf] RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS Applications
270 [Zamdmer] [pdf] Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits
271 [Gondro] [pdf] Influence of the Inner Miller-Effect on the Input Capacitance of CMOS Transistors
272 [Lee3] [pdf] High Hot-Carrier and ESD Immunity Device for High-Voltage I/O NMOSFETs in 0.1-um CMOS Technology
273 [Ahmed] [pdf] Scaling of MOSFET Transconductance with Gate Oxide Thickness and Effect of Remote Charge Scattering
274 [Ionescu] [pdf] A Novel MEMS Technological Platform Aimed at RF Applications
275 [Dimitrakis] [pdf] Si Nanocrystal Based Memory Structures by Ultra Low Energy Implantation for Low Voltage/Low Power Applications
276 [Yuan] [pdf] Source/Drain Parasitic Resistance Role and Electrical Coupling Effect in sub 50nm MOSFET Design
277 [Sotiriadis] [pdf] Fast Algorithm for Clock Grid Simulation

269 papers