Tuesday 24 Sept. 2002

Session P1: Keynote presentation
Session DP1: ESSDERC Plenary presentation
Session D1: Noise analysis
Session D2: CMOS channel engineering
Session D3: MOSFET technology
Session P2: Keynote presentation
Session D4: Emerging modeling topics
Session D5: Advanced gate oxide techniques
Session D6: Advanced Si-Ge devices
Session D7: Monte Carlo device analysis
Session D8: Shallow junction technology
Session D9: Advanced III-V devices

Wednesday 25 Sept. 2002

Session P3: Keynote presentation
Session DP2:  ESSDERC Plenary presentation
Session D10: Characterization techniques
Session D11: RF process modules
Session D12: Power devices
Session P4: Keynote Presentation
Session D13: Modeling of advanced devices
Session D14:  Junction Engineering
Session D15: New device concepts
Session D16: Analysis of doping effects
Session D17: Non-volatile memories
Session D18: RF and novel devices

Thursday 26 Sept. 2002

Session P5: Keynote Presentation
Session DP3: ESSDERC Plenary presentation
Session D19: Modeling of quantum devices
Session D20: High K dielectrics
Session D21: Physical sensors
Session P6: Keynote presentation
Session D22: Modeling of power devices
Session D23: New memory technologies
Session D24: Biosensors and microfluidics
Session D25: MOSFET modeling
Session D26: SOI and isolation techniques
Session D27: Organic electronics and TFT's

All days 13:50 to 14:20

Poster Session

Room: Auditorium

08.50 Introduction
Giorgio Baccarani, ESSDERC 20002 Chairman
Rinaldo Castello, ESSCIRC 2002 Chairman

Session P1: Keynote presentation

Chairmans:
Giorgio Baccarani, University of Bologna, Bologna, Italy
Rinaldo Castello, University of Pavia, Pavia, Italy

09.00 Invited Paper

Nanoscale System Design Challenges: business as usual?

Hugo De Man
IMEC, Leuven, Belgium

While process technologists pursue Moore's curve down to nanoscale dimensions, designers are confronted with gigascale complexity. In addition, post-PC products require zero cost, zero energy yet software programmable architectures to be designed in exponentially decreasing time. How do we cope with these novel silicon architectures? How do we create the necessary tools and skills and how to organise research and education in a world driven by shareholders value.

Session DP1:  ESSDERC Plenary presentation

Chairman:
G. Baccarani, University of Bologna, Bologna, Italy

09.50 Invited Paper

Imagine the Future in Telecommunications Technology
D. Harame¹, A. Joseph¹, D. Coolbaugh¹, G. Freeman², D. Greenberg³, M. Ritter³, K. Newton¹, S. M. Parker¹, R. Groves², H.Zamat⁴, V.S.Marangos⁵, M.M.Doherty⁵, O. Schreiber⁶,T. Tanji⁷, D. A. Herman², M. Meghali³, R. Singh¹

¹IBM, Essex Jct, United Sates
²IBM, Hopewell Junction, United Sates
³IBM, Yorktown Heights, United Sates
⁴IBM, Encinitas, United Sates
⁵IBM, Massachusetts, United Sates
⁶AMCC, San Diego, United Sates

The complexity of RF Analog and Mixed Signal products continues to increase as we progress towards more highly integrated chips to satisfy the exploding wired (networking) and wireless areas. We now have technologies (SiGe BiCMOS and RFCMOS) that can satisfy the requirements of these areas but are still challenged in modeling and design automation. IBM’s SiGe BiCMOS Technologies are described.

10.30 to 10.50 Coffee Break

Room: Auditorium

Session D1: Noise analysis

Chairmans:
Reinout Woltjer, Philips, Eindhoven, The Netherlands
Massimo Rudan, University of Bologna, Bologna, Italy

D1.1
10.50 Noise Analysis for a SiGe HBT by Hydrodynamic Device Simulation
C. Jungemann, B. Neinhues, B. Meinerzhagen
University of Bremen, Germany

D1.2
11.10 On the origin of the 1/f^1.7 noise in deep submicron partially depleted SOI transistors
N. Lukyanchikova¹, M. Petrichuk¹, N. Garbar¹, E. Simoen², A. Mercha², H. van Meer², K. De Meyer², C. Claeys^2
1Institute of Semiconductor Physics, Kiev, Ukraine
²IMEC, Leuven, Belgium

D1.3
11.30 Inversion Layer Quantization Impact on the Interpretation of 1/f Noise in Deep Submicron CMOS Transistors
A. Mercha, E. Simoen, G. Richardson, C. Claeys
IMEC, Leuven, Belgium

D1.4
11.50 Constant and Switched Bias Low Frequency Noise in p-MOSFETs with Varying Gate Oxide Thickness
J. S. Kolhatkar¹, C. Salm¹, M.J. Knitel², H. Wallinga^1
1University of Twente, Enschede, The Netherlands
²Philips Research, The Netherlands

D1.5
12.10 Investigation of the Thermal Noise of MOS Transistors under
R. Brederlow¹, G. Wenig², R. Thewes^1
1Infineon Technologies, Muenchen, Germany
²Technical University Munich, Germany

D1.6
12.30 Measurement of MOSFET LF Noise Under Large Signal RF Excitation
A. P. van der Wel, E. A. M. Klumperink, B. Nauta
University of Twente, Enschede, The Netherlands

Room: Sala Onice

Session D2: CMOS channel engineering

Chairmans:
Martin Kerber, Infineon, Munich, Germany
Maurizio Severi, CNR, Bologna, Italy

D2.1
10.50 Invited Paper

Impact of Parametric Fluctuations on Performance and Yield of Deep-Submicron Technologies
Hans Tuinhout
Philips Research, Eindhoven, The Netherlands

D2.2
11.30 A Tuneable Metal Gate Work Function Using Solid State Diffusion of Nitrogen
R. Lander¹, J. Hooker¹, J. van Zijl², F. Roozeboom², M. Maas², Y. de Tamminga³, R. Wolters^2
1Philips Research Leuven, Belgium
²Philips Research Laboratories, Eindhoven, The Netherlands
³Philips CFT, Eindhoven, The Netherlands

D2.3
11.50 Gate oxide process impact on RNCE for advanced CMOS transistors
F. Arnaud¹, M. Bidaud^2
1STMicroeletronics, Crolles, France
²Philips Semiconductors, France

D2.4
12.10 Post-Process CMOS Front End Engineering With Focused Ion Beams
A. Lugstein¹, W. Brezna¹, B. Goebel², L. Palmetshofer³, E. Bertagnolli^1
1Technical University Vienna, Austria
²Infineon
³Technical University Linz, Austria

D2.5
12.30 Impact of source/drain implants on threshold voltage matching in deep sub-micron CMOS technologies
J. Dubois¹, J. Knol¹, M. Bolt¹, H. Tuinhout², J. Schmitz², P. Stolk^2
1Philips Semiconductors, Nijmegen, The Netherlands
²Philips Research, The Netherlands

Room: Sala 4

Session D3: MOSFET technology

Chairmans:
Hiroshi Iwai, Tokyo Inst. of Technology, Yokohama, Japan
Simon Deleonibus, LETI, Grenoble, France

 D3.1
10.50 Channel Engineering Study for 50 nm P-Channel MOSFET
G. Guegan¹, D. Souil¹, S. Deleonibus¹, S. Tedesco¹, C. Laviron¹, P. Previtali¹, M. E. Nier^2
1CEA/LETI, Grenoble, France
²ST-Microelectronics, France

D3.2
11.10 SiGe pMOSFETs Fabricated on Novel SiGe Virtual Substrates Grown on 10µm x 10µm Pillars
U. Straube¹, A. Waite¹, N. Lloyd¹, S. Croucher¹, Y. Teng Tang¹, A. Evans¹, T. Grasby², T. Whall², E. Parker², D. Norris³, T. Cullis^3
1University of Southampton, United Kingdom
²University of Warwick, United Kingdom
³University of Sheffield, United Kingdom

D3.3
11.30 Investigations on Poly-SiGe gate in full 0.1µm CMOS integration
B. Tavel¹, F. Monsieur², P. Ribot², T. Skotnicki^2
1France Telecom R&D, France
²STMicroelectronics, France

D3.4
11.50 65 nm Transistors for a 90 nm CMOS SOC Platform
M. R. Mirabedini, V. P. Gopinath, A. Kamath, M. Y. Lee, W. C. Yeh
LSI Logic Corporation, Santa Clara, United States

D3.5
12.10 Influence of source-drain tunneling on the subthreshold behavior of sub-10nm double-gate MOSFETs
M. Staedele
Infineon Technologies, Munich, Germany

D3.6
12.30 Understanding nMOSFET characteristics after soft breakdown and their dependence on the breakdown location
B. Kaczer¹, R. Degraeve¹, F. Crupi², A. De Keersgieter¹, G. Groeseneken^1
1IMEC, Leuven, Belgium
²University of Messina, Messina, Italy

12.50 to 13.50 Lunch

13.50 to 14.20 Poster Session

Room: Auditorium

Session P2: Keynote Presentation

Chairmans:
Rinaldo Castello, University of Pavia, Pavia, Italy
Willy Sansen, KU Leuven, Belgium

14.20 Invited Paper

High-speed converters for telecom applications
R. Van de Plassche
Broadcom, The Netherlands

Room: Sala Verde

Session D4: Emerging modeling topics

Chairman:
Gerhard Wachutka, TU Munich, Munich, Germany

 D4.1
15.10 Accurate Delay Metric for On-chip Resistive Interconnect
M. Oulmane, N. Rumin
McGill University, Montreal, Canada

D4.2
15.30 A new approach to failure analysis and yield enhancement of very large-scale integrated systems
S. Amakawa¹, K. Nakazato², H. Mizuta^2
1University of Cambridge, United Kingdom
²Hitachi Europe Ltd., United Kingdom

D4.3
15.50 Three-Dimensional Analysis of a MAGFET at 300 K and 77 K
R. Rodríguez-Torres¹, E. A. Gutiérrez-D. ², R. Klima¹, S. Selberherr^1
1Institute for Microelectronics, TU Wien, Austria
²MCST, Motorola-SPS, Mexico

Room: Sala Onice

Session D5: Advanced gate oxide techniques

Chairman:
Stefan Bengtsson, Chalmers University, Göteborg, Sweden

D5.1
15.10 Triple Gate Oxide by Nitrogen Implantation Integrated in a 0.13µm CMOS Flow
J. P. Carrčre¹, A. Grouillet², F. Guyader¹, A. Beverina¹, M. Bidaud³, A. Halimaoui^1
1ST Microelectronics, Crolles Cedex, France
²France Télécom R&D, France
³Philips Semiconductors, France

D5.2
15.30 RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS Applications
A. Veloso¹, M. Jurczak¹, F. Cubaynes², R. Rooyackers¹, S. Mertens¹, A. Rothschild¹, M. Schaekers¹, H. Al-Shareef³, R. Murto³, C. Dachs², G. Badenes^1
1IMEC, Leuven, Belgium
²Philips Research, Leuven, Belgium
³International Sematech, Austin-TX, USA

D5.3
15.50 Thermal Nitridation of Chemical Dielectrics as an Easy Approach to Ultra-thin Gate Oxide Processing
M. Bidaud¹, J. P. Carrčre², F. Guyader², M. Juhel², R. Pantel^2
1Philips Semiconductors, Crolles Cedex, France
²ST Microelectronics, France

Room: Sala 4

Session D6: Advanced Si-Ge devices

Chairman:
Jan Slotboom, Philips, Eindhoven, The Netherlands

D6.1
15.10 Gate length scaling in high fMAX Si/SiGe n-MODFET
F. Anie¹, M. Enciso-Aguilar¹, P. Crozat¹, R. Adde¹, T. Hackbarth², U. Seiler², H-J. Herzog², U. Konig², H. von Kanel^3
1IEF, Orsay, France, Metropolitan
²DaimlerChrysler Research Center, Germany
³ETH Zurich, Switzerland

D6.2
15.30 Application of Polycrystalline SiGe for Gain Control in SiGe Heterojunction Bipolar Transistors
V. D. Kunz¹, C. H. de Groot¹, S. Hall², I. M. Anteney¹, A. I. Abdul-Rahim¹, P. Ashburn^1
1University of Southampton, United Kingdom
²University of Liverpool, United Kingdom

D6.3
15.50 Enhanced intrinsic gain (gm/gd) of PMOSFETs with a Si(0.7)Ge(0.3) channel
A. C. Lindgren, P. E. Hellberg, M. von Haartman, D. Wu, C. Menon, S. Zhang, M. Östling
Royal Institute of Technology, Kista, Sweden

16.10 to 16.30 Coffee Break

Room: Sala Verde

Session D7: Monte Carlo device analysis

Chairman:
Bern Meinerzhagen, University of Bremen, Bremen, Germany

D7.1
16.30 Efficient Monte Carlo Simulation of Tunnel Currents in MOS Structures
D. Grgec¹, M. Vexler², C. Jungemann¹, B. Meinerzhagen^1
1University of Bremen, Germany
²A.F.Ioffe Physicotechnical Institute, St. Petersburg, Russia

D7.2
16.50 An Improved Model for Electron Mobility Degradation by Remote Coulomb Scattering in Ultra-Thin Oxide MOSFETs
D. Esseni, A. Abramo
DIEGM, University of Udine, Italy

D7.3
17.10 Monte Carlo Simulation of Program and Erase Charge Distributions in NROM(TM) Devices
G. Ingrosso, L. Selmi, E. Sangiorgi
DIEGM, University of Udine, Italy

D7.4
17.30 Investigation on Convergence and Stability of Self-Consistent Monte Carlo Device Simulations
R. Clerc, P. Palestri, A. Abramo
DIEGM, University of Udine, Italy

Room: Sala Onice

Session D8: Shallow junction technology

Chairmans:
Corrado Rosario Spinella, CNR - IMETEM, Catania, Italy
Marc Heyns, IMEC, Leuven, Belgium

D8.1
16.30 Suppression of CoSix Induced Leakage Current using Novel Capping Process for Sub-0.10um node SRAM Cell technology
H. Kwon, B. Hwang, W. Cho, C. Chang, S. Kim, Y. Park, H. Ihm, J. K. Park, H. Kang, J. Jeong, J. B. Park, Y. Jang, S. Yung, K. Kim
Semiconductor R&D center, Samsung Electronics, Kyungki-Do, Korea (South)

D8.2
16.50 Antimony as Substitute for Arsenic to Eliminate Enhanced Diffusion Effects
H. Rucker, B. Heinemann, R. Barth, D. Bolze, V. Melnik, R. Kurps, D. Kruger
IHP, Frankfurt, Germany

D8.3
17.10 Diffusion Suppression in Silicon by Substitutional C Doping
N. Cowern¹, B. Colombeau¹, F. Roozeboom², M. Hopstaken², H. Snijders², P. Meunier³, W. Lerch^4
1University of Surrey, Surrey, United Kingdom
²Philips Research, Eindhoven, The Netherlands
³Philips Research/IMEC, Leuven, Belgium
⁴Mattson Thermal Products GmbH, Dornstadt, Germany

D8.4
17.30 Spike anneal optimization for digital and analogue high performance 0.13 µm CMOS platform
E. Josse, F. Arnaud, F. Wacquant, D. Lenoble, O. Menut, E. Robilliart
STMicroelectronics, Crolles, France

Room: Sala 4

Session D9: Advanced III-V devices

Chairmans:
Peter Ashburn, University of Southampton, United Kingdom
Gehan Amaratunga, Cambridge University, United Kingdom

D9.1
16.30 Pseudo Dynamic Gate Design based on the Resonant Tunneling-Bipolar Transistor (RTBT)
P. Gloesekoetter¹, C. Pacha², W. Prost³, S. Kim⁴, H. van Husen³, T. Reimann³, F. J. Tegude³, K. F. Goser^1
1University of Dortmund, Germany
²Infinion Technologies, Munich, Germany
³University of Duisburg, Germany
⁴Ferdindnand-Braun-Institut für Hoechstf., Berlin, Germany

D9.2
16.50 On the n+-GaAs/p+-InGaP/n--GaAs High-Barrier Camel-Like Gate Transistor for High-Breakdown, Low-Leakage and High-Temperature Operations
W. C. Liu, K. H. Yu, H. M. Chuang, K. W. Lin, K. M. Lee, S. F. Tsai
Inst. Microelectronics, Dept. E.E., Taiwan

D9.3
17.10 An InGaP/GaAs Resonant-Tunnelling Bipolar Transistor (RTBT) with Multiple Negative-Differential-Resistance (MNDR) Phenomena
H. M. Chuang, K. W. Lin, H. J. Pan, K. M. Lee, X. D. Liao, W. C. Liu
Inst. Microelectronics, Dept. E.E., Taiwan

D9.4
17.30 Self Heating in InP DHBT Technology for 40 Gb/s ICs
L. Giguerre¹, M. Abboun¹, F. Aniel¹, N. Zerounian¹, A. Dubois¹, R. Adde¹, S. Blayac², M. Riet², A. Konczykowska^2
1IEF, Paris-South University, Orsay Cedex, France
²OPTO+/Alcatel R&I, Marcoussis, France

Room: Auditorium

08.50 Best Paper Award
Gerhard Wachutka, TU Munich, Germany
Franz Dielacher, AMS, Austria

Chairmans:
Gilbert Declerck, IMEC, Leuven, The Netherlands
Franz Dielacher, AMS, Austria

09.00 Invited Paper

In recent years there has been a great effort in biology, chemistry and engineering to pursue the advantages of miniaturization for cheaper better faster sample analysis. So far, the aim has been mainly the speed-up of DNA amplification and detection and other molecular analysis from preprocessed samples. To attain the pervasiveness enjoyed today by electronic devices, a much higher degree of functional integration will be required, for the new goal of sample-to-answer systems. This presentation will discuss the main challenges and unmet needs to seize the opportunities existing for cheap and ubiquitous bioanalytical devices, and how microelectronic technology could play a leading role.

09.50 Invited Paper

Current status of silicon single-electron devices for logic applications is reported. The device has a unique feature such as low-power consumption nature, capability of supporting multiple-gate, and multipeak oscillatory characteristics. We have exploited these features to achieve complicated functions, such as an adder and a multiple-valued circuit. In addition, we have developed a new device called single-electron CCD that also enables us to manipulate a single electron.

Room: Aiutorium

Chairmans:
Siegfried Selberherr, TU Wien, Vienna, Austria
Enrico Sangiorgi, Univeristŕ di Udine, Udine, Italy

D10.1
10.50 Extraction method for the impact-ionization multiplication factor in silicon at large operating temperatures
E. Gnani, S. Reggiani, M. Rudan, G. Baccarani
ARCES-DEIS, Univiversity of Bologna, Italy

D10.5
12.10 A method for extraction of power dissipating sources from interferometric thermal mapping measurements
D. Pogany¹, M. Litzenberger¹, S. Bychikhin¹, E. Gornik¹, G. Groos², M. Stecher^2
1Institute for Solid State Electronics, TU Vienna, Austria
²Infineon Technologies, Munich,Germany

D10.6
12.30 Universal Test Structure and Characterization Method for Bias-Dependent Drift Series Resistance of HV MOSFETs
C. Anghel¹, N. Hefyene¹, A. IONESCU¹, S. Frere², R. Gillon², J. Rhayem^2
1EPFL, Lausanne, Switzerland
²Alcatel Microelectronics, Belgium

Room: Sala Onice

Chairmans:
Mikael Östling, KTH, Royal Institute of Technology, Kista, Sweden
Joachim Burghartz, DIMES, Delft, The Netherlands

D11.1
10.50 Impact of Deep N-well Implantation on Substrate Noise Coupling and RF Transistor Performance for Systems-on-a-Chip Integration
K. Wai Chew, J. Zhang, K. Shao, W. Boon Loh, S.-Fu Chu
Chartered Semiconductor Manufacturing Ltd, Singapore

D11.3
11.30 A Self-Aligned Double Poly-Si Process Utilizing Non-Selective Epitaxy of SiGe:C for Intrinsic Base and Poly-SiGe for Extrinsic Base
J. Pejnefors¹, T. Johansson², J. Wittborn², A. Santos², H. Norström², U. Smith², A. Cheshire³, T. Buschbaum⁴, C. Rosenblad⁴, J. Ramm^4
1Royal Institute of Technology (KTH)-IMIT, Kista, Sweden
²Ericsson Microelectronics AB, Sweden
³Applied Materials UK Ltd., United Kindom
⁴Unaxis Balzers Ltd., Liechtenstein

D11.4
11.50 Influence of the Ge-concentration and RTA on the device performance of strained Si/SiGe pMOS devices
N. Collaert, P. Verheyen, K. De Meyer, R. Loo, M. Caymax
¹IMEC, Heverlee, Belgium

D11.5
12.10 Use of Oxynitride Dielectric to Maximise the Growth Rate of Selective Epitaxial Base Layer in a Self-Aligned Double-Polysilicon SiGe Bipolar Transistors
J. Ackaert, P. Chevalier, J.-L. Loheac, H. Ziad, E. De Backer, M. Tack
Alcatel Microelectronics, Oudenaarde, Belgium

Room: Sala 4

Chairmans:
Steffi Lindenkreuz, Bosch, Germany
Marnix Tack, Alcatel Microelectronics, Oudenaarde, Belgium

D12.2
11.30 Lateral Trench Gate Super-Junction SOI-LDMOSFETs with Low On-Resistance
J. Mun Park, R. Klima, S. Selberherr
Institute for Microelectronics, TU Wien,  Austria

D12.4
12.10 Cost Effective Implementation of a 90 V RESURF P-type Drain Extended MOS in a 0.35 um Based Smart Power Technology
B. Bakeroot¹, M. Vermandel¹, P. Moens², J. Doutreloigne¹, D. Bolognesi^2
1ELIS-TFCG/IMEC University of Gent, Belgium, Belgium
²Alcatel Microelectronics, Oudenaarde, Belgium

13.50 to 14.20 Poster Session

Room: Auditorium

Session P4: Keynote Presentation

Chairmans:
Gerhard Wachutka, TU Munich, Munich, Germany
Eric Vittoz, CSEM, Neuchâtel, Switzerland

Chairman:
Asen Asenov, University of Glasgow, Glasgow, United Kingdom

D13.1
15.10 Exploring Methods for Adequate Simulation of Sub-100nm Devices
V. Moroz¹, N. Strecker¹, M. Jaraiz^2
1Avanti Corp., Fremont, CA, United States
²University of Valladolid, Valladolid, Spain

D13.2
15.30 Tunnelling and impact ionization in scaled double doped PHEMTs
K. Kalna, A. Asenov
University of Glasgow, United Kingdom

D13.3
15.50 Accurate Modelling of Thin-Film Resistor up to 40 GHz
Z. Wang¹, J. Deen¹, A. Rahal^2
1Dept. of ECE, McMaster University, Ontario, Canada
²Nanowave Inc., Canada

Chairmans:
Joerg Osten, Inst. For Semiconductor Dev. and Electr. Materials, Hannover, Germany
Pierre Fazan, EPFL, Lausanne, Switzerland

D14.2
15.30 Advanced Junction Engineering for 60nm-CMOS Transistors
M. Müller¹, M. Bidaud¹, F. Boeuf², A. Halimaoui², M. Lamy², D. Lenoble², R. Palla², T. Skotnicki², C. Laviron^3
1Philips Semiconductors, Crolles, France
²ST Microelectronics, France
³CEA/LETI-Grenoble, France

D14.3
15.50 High performance 0.1um CMOS device with suppressed parasitic junction capacitance and junction leakage current
H. Sik Kim, S. Mani Pandey, S. Yang Ong, M. Sarkar, Y. Way Teh, F. Benistant, E. Quek, M. Bhat, S. Chu
Chartered Semiconductor Manufacturing Ltd., Sigapore, Singapore

Room: Sala 4

Chairman:
Kristin de Meyer, IMEC, Leuven, Belgium

D15.1
15.10 The Four-Gate Transistor
S. Cristoloveanu¹, B. Blalock², F. Allibert³, B. Dufrene⁴, M. Mojarradi^5
1IMEP, Grenoble, France
²University of Tennessee, United States
³SOITEC, France
⁴Mississippi State University, United States
⁵Jet Propulsion Lab, United States

D15.3
15.50 Voltage-controlled substrate structure for integrated inductors in standard digital CMOS technologies
J. Maget^1,2, R. Kraus¹, M. Tiebout^2
1University of Bundeswehr, Munich, Germany
²Infineon Technologies, Munich, Germany

Room: Sala Verde

Chairmans:
Dimitris Tsoukalas, IMEL/NCRS, AGHIA PARASKEVI, Greece
Hervé Jaouen, St-Microelectronics, Crolles, France

D16.2
16.50 Three-dimensional simulation of the channel stop implant effects in sub-quarter micron PMOS transistors
A. Burenkov, J. Lorenz
Fraunhofer Institute of Integrated Circuits, Erlangen, Germany

D16.4
17.30 On Increasing the Accuracy of Simulations of Deposition and Etching Processes Using Radiosity and the Level Set Method
C. Heitzinger¹, J. Fugger², O. Häberlen², S. Selberherr^1
1Institute for Microelectronics, Vienna, Austria
²Infineon Technologies, Villach, Austria

Chairmans:
Paolo Cappelletti, St-Microelectronics, Agrate, Italy
Guido Groesenecken, IMEC, Leuven, Belgium

Room: Sala 4

Session D18: RF and novel devices

Chairmans:
Sorin Cristoloveanu, LPCS/INPG, Grenoble, France
Joachim Burghartz, DIMES, Delft, The Netherlands

D18.2
16.50 Design Guidelines for Linear Amplification and Low-insertion loss in 5-GHz-band SOI Power MOSFETs
S. Matsumoto, Y. Hiraoka, M. MIno
NTT Telecommunications Energy Laboratories, Atsugi, Japan

D18.3
17.10 A 12Volt, 12GHz Complementary Bipolar Technology for High Frequency Analogue Applications
M. C. Wilson, S. Nigrin, S. Harrington, S. Manson, S. Thomas, L. Benton, S. Connor, P. Osborne
Zarlink Semiconductor, United Kingdom

Room: Auditorium

08.50 Presentation of 2003 Edition
Jose Epifanio da Franca, ESSDERC/ESSCIRC 2003 Chairman
Peter Ashburn, University of Southampton, United Kingdom

Session P5: Keynote Presentation

Chairmans:
Peter Ashburn, University of Southampton, United Kingdom
Jose Epifanio da Franca, University of Lisbon, Portugal

Room: Auditorium

Chairman:
Peter Ashburn, University of Southampton, United Kingdom

Materials, Devices and Circuit Applications of Si-based Optoelectronics
S. Coffa, St-Microelectronics, Italy

Room:  Auditorium

Chairman:
Wim Schoenmaker, IMEC, Leuven, Belgium

D19.1
10.50 Invited Paper

Quantum Computation and Proposal for Solid-state quantum Gates
A. Bertoni^1,2, S. Reggiani^1
1ARCES-DEIS, University of Bologna, Italy
²INFM, Modena, Italy

D19.2
11.30 Quasi-analytical modelling of drain current and conductance of Single Electron Transistors with MIB
Santanu Mahapatra¹, Adrian Mihai Ionescu¹, Kaustav Banerjee^2
1LEG-EPFL,Switzerland, Switzerland
²CIS-Stanford, USA

D19.3
11.50 Coulomb Blockade in Thin SOI Nanodevices
D. Fraboulet¹, X. Jehl², D. Mariolle¹, C. Le Royer¹, G. Le Carval¹, P. Scheiblin¹, P. Rivallin¹, L. Mollard¹, D. Deleroyelle¹, M. E. Nier¹, A. Toffoli¹, G. Molas¹, B. De Salvo¹, S. Deleonibus¹, M. Sanquer^2
1CEA-LETI, GRENOBLE, France
²CEA-DRFMC, France

D19.4
12.10 Tunnel Barrier Properties of Polycrystalline-Si Single-Electron Transistor
Y. Furuta¹, H. Mizuta¹, T. Kamiya², Y. Tan², K. Nakazato¹, Z. Durrani², K. Taniguchi^3
1Hitachi Cambridge Laboratory, United Kingdom
²MRC, Cavendish Laboratory, United Kingdom
³Osaka University, Japan

D19.5
12.30 Accurate modeling of Quantum-Dot based Multi Tunnel Junction Memory: Optimization and process dispersions analyzes for DRAM applications
C. Le Royer¹, G. Le Carval¹, D. Fraboulet¹, M. Sanquer^2
1CEA-LETI, Grenoble, France
²CEA-DRFMC, France

Room: Sala Onice

Chairmans:
Livio Baldi, St-Microelectronics, Agrate, Italy
Robert Lander, Philips, Leuven, Belgium

D20.1
10.50 Process Integration of Crystalline Pr₂O₃ High-k Gate Dielectrics
U. Schwalke¹, K. Boye¹, G. Hess¹, G. Muller¹, K. Haberle¹, R. Heller¹, T. Rulan¹, G. Tzschockel¹, J. Osten², A. Fissel², H.-J- Mussig^2
1Technical Univ. Darmstadt, Germany
²IHP, Germany

D20.2
11.10 Investigation of HfO2 dielectric stacks deposited by ALD with a mercury probe
X. Garros¹, C. Leroux², D. Blin³, J.-F. Damlencourt², A.-M. Papon², G. Reimbold^2
1CEA-LETI/STMicroelectronics, Grenoble, France
²CEA-LETI, France
³CEA-LETI/ASM France

D20.3
11.30 Electrical Characteristics of Gd2O3 thin film deposited on Si substrate
C. Ohshima, I. Kashiwag, S.-I. Ohmi, H. Iwai
Tokyo Institute of Technology, Yokohama-shi, Japan

D20.4
11.50 ZrO2 gate dielectrics prepared by e-beam deposition of Zr and YSZ films and post annealing processes
M. Johansson¹, M. Y. A. Yousif¹, A. Sareen¹, P. Lundgren¹, S. Bengtsson¹, U. Sodervall^2
1Solid State Electronics, Chalmer Univ, Sweden, Sweden
²SIMS Laboratory, Chalmer Univ, Sweden

D20.5
12.10 Characteristics of HfO2 pMOSFET with ultrashallow junction prepared by plasma doping and laser annealing
S. Baek, S. Heo, H. Hwang
Kwangju Institute of Science and Technology, Korea (South)

D20.6
12.30 Gate dielectrics for high performance and low power CMOS SoC applications
F. Cubaynes¹, C. Dachs¹, C. Detcheverry¹, A. Zegers², V. Venezia¹, J. Schmitz¹, P. Stolk¹, M. Jurczak³, K. Henson³, R. Degraeve³, A. Rothschild³, T. Conard³, J. Petry³, M. Da Rold³, M. Schaekers³, G. Badenes³, L. Date⁴, D. Pique⁴, H. Al-Shareef⁵, R. Murto^5
1Philips Research, Leuven, Belgium
²Philips Research, Heindoven, The Netherlands
³IMEC, Belgium
⁴Applied Materials, France⁵
International Sematech, United States

Room: Sala 4

Chairmans:
Benedetto Vigna, St-Microelectronics, Cornaredo, Italy
Lina Sarro, DIMES, Delft, The Netherlands

D21.1
10.50 A CMOS Photodiode Array with Linearized Spectral Response and Spatially Distributed Light Intensity Detection for the Use in Optical Storage Systems
I. Hehemann¹, E. Özkan¹, A. Kemna¹, W. Brockherde¹, B. J. Hosticka¹, H. Hofmann^2
1Fraunhofer IMS, Duisburg, Germany
²Thomson Multimedia, Germany

D21.2
11.10  Fast CMOS-Integrated Finger Photodiodes for a Wide Spectral Range
H. Zimmermann¹, A. Ghazi², H. Dietrich¹, P. Seegebrecht^2
1Technische Universität Wien, Vienna, Austria
²Christian-Albrechts-Universität, Kiel, Germany

D21.3
11.30 Quantum Dot Materials and Devices for Light Emission in Silicon
M. E. Castagna¹, S. Coffa¹, L. Caristia¹, A. Messina¹, C. Bongiorno^2
1STMicroelectronics, Catania, Italy
²CNR IMETEM, Catania, Italy

D21.4
11.50 Micromachined Mercury Sensor
Kwan Schambach¹, Klaus Eden², Klaus Schumacher³, Gerhard Wiegleb^2
1Geminuse G., Dortmund, Germany
²University of Applied Sciences Dortmund, Germany
³University of Dortmund, Germany

D21.5
12.10 Clamped-Clamped Beam Micro-Mechanical Resonators in Thick-Film Epitaxial Polysilicon Technology
D. Galayko¹, A. Kaiser¹, B. Legrand¹, L. Buchaillot¹, C. Combi², D. Collard^3
1IEMN-ISEN UMR CNRS 8520, Lille, France
²ST Microelectronics, Milan, Italy
³CIRMM/ISS-The University of Tokyo, Japan

D21.6
12.30 Monolithic Integration of a Novel Microfluidic Device with Silicon Light Emitting Diode-Antifuse and Photodetector
P. LeMinh, J. Holleman, J. Berenschot, N. Tas, A. van den Berg
MESA+ Research Institute, University of Twente, Enschede, The Netherlands

Room: Auditorium

Session P6: Keynote presentation

Chairmans:
Massimo Rudan, University of Bologna, Italy
Andrea Baschirotto, University of Pavia, Italy

Prospects for Single Molecule Information Devices
Y. Wada
Hitachi, Japan

Present information technologies will face fundamental limitations within a decade, and superseding devices are required for the next paradigm of high performance information technologies. This paper describes prospects for single molecule devices suitable for future information processing technologies. Possible four milestones for realizing the Peta/Exa-floating operations per second (FLOPS) personal molecular supercomputer are proposed. Current status and necessary technologies of the first milestone are described, and necessary technologies for the next three milestones are also discussed.

Room: Sala Verde

Chairman:
Gehan Amaratunga, Cambridge University, United Kingdom

D22.1
15.10 A Robust and Physically Based Compact SOI-LDMOS Model
A. Aarts, R. van Langevelde
Philips Research Laboratories, Eindhoven, Netherlands

D22.2
15.30 UIS-Failure of DMOS Power Transistors
A. Icaza Deckelmann¹, G. Wachutka¹, F. Hirler², J. Krumrey^2
1Institute for Physics of Electrotechnology, Munchen, Germany
²Infineon Technologies, Munich, Germany

D22.3
15.50 Temperature dependence of the hard breakdown current of MOS capacitors
A. Avellan¹, E. Miranda², B. Sell³, D. Schroeder¹, W. Krautschneider^1
1Technische Universitaet Hamburg-Harburg, Germany
²Universidad de Buenos Aires, Argentina
³Infineon Technologies AG

Room: Sala Onice

Chairman:
Herman Maes, IMEC, Leuven, Belgium

D23.1
15.10 A Viable Self-aligned Bottom-Gate MOSFET Technology for High Density and Low Voltage SRAM
S. Zhang¹, Z. Zhang¹, X. Lin¹, R. Han², P. K. Ko¹, M. Chan^1
1Dept. of EEE, HKUST, Hong Kong, China
²Peking University, China

D23.2
15.30 Electrical Characterisation of Silicon-Rich-Oxide Based Memory Cells Using Pulsed Current-Voltage Techniques
M. Rosmeulen^1,2, E. Sleeckx², K. De Meyer^1,2
1KU Leuven, Belgium
²IMEC, Leuven, Belgium

D23.3
15.50 Reliability and Retention Study of Nanocrystal Cell Array
C. Gerardi¹, G. Ammendola¹, M. Melanotte¹, S. Lombardo², I. Crupi^2,3
1STMicroelectronics, Catania, Italy
²CNR-IMM, Italy
³INFM, Italy

Room: Sala 4

Chairmans:
Roland Thewes, Infineon, Munich, Germany
Dominique Collard, ISEN, Villeneuve d'Ascq Cedex, France

D24.1
15.10 A Biosensor for Direct Detection of DNA Sequences Based on Capacitance Measurements
C. Guiducci¹, C. Stagni¹, G. Zuccheri², A. Bogliolo³, L. Benini¹, B. Samorě², B. Riccň^1
1DEIS-University of Bologna, Italy
²Department of Biochemistry, University of Bologna, Italy
³STI-University of Urbino, Italy

D24.2
15.30 Array-Based Electrical Detector of Integrated DNA Identification System for Genetic Chip Applications
M. Xue¹, J. Li², Z. Lu², P. Ko³, M. Chan^3
1Hong Kong Univ. of Sci. & tech., China
²Southeast University, China
³Hong Kong Univ. of Sci. & tech., China

D24.3
15.50 Passive DNA Sensor with Gold Electrodes Fabricated in a CMOS Backend Process
F. Hofmann¹, A.r Frey¹, B. Holzapfl¹, M. Schienle¹, C. Paulus¹, P. Schindler-Bauer¹, R. Thewes¹, R. Hintsche², E. Nebling², J. Albers², W. Gumbrecht^3
1Infineon Technologies, Munich, Germany
²Fraunhofer Gesellschaft, Germany
³Siemens, Germany

Room: Sala Verde

Chairman:
Bernd Meinerzhagen, Un. Bremen, Germany

D25.1
16.30 The RF potential of high-performance 100nm CMOS technology
V. Charles Venezia¹, A. J. Scholten², C. Detcheverry¹, H. Boots¹, W. Jeamsaksin³, L. Grau³, D. B.M. Klaassen², R. M.D.A. Velghe¹, R. J. Havens², L. F. Tiemeijer^2
1Philips Research Leuven, Belgium
²Philips Research, Eindhoven, The Netherlands
³IMEC, Belgium

D25.2
16.50 CMOS circuit analysis with luminescence measurements and simulations
F. Stellari¹, A. Tosi², F. Zappa², S. Cova^2
1IBM T.J. Watson Research Center, United States
²Politecnico di Milano – DEI, Italy

D25.3
17.10 Investigating 50nm channel length vertical MOSFET containing a dielectric pocket, in a circuit environment
D. C. Donaghy¹, S. Hall¹, D. Kunz², K. de Groot², P. Ashburn^2
1University of Liverpool, United Kingdom
²University of Southampton, United Kingdom

D25.4
17.30 Source/Drain Parasitic Resistance Role and Electrical Coupling Effect in sub 50nm MOSFET Design
J. Yuan¹, P. M. Zeitoff², J. C. S. Woo^1
1 University of California, Los Angeles, United States
²SEMATECH, United States

Room: Sala Onice

Session D26: SOI and isolation techniques

Chairmans:
Lothar Risch, Infineon, Munich, Germany
Thomas Skotnicki, St-Microelectronics, Crolles Cedex, France

D26.1
16.30 Controlling STI-related parasitic conduction in 90 nm CMOS and below
E. Augendre¹, R. Rooyackers¹, D. Shamiryan¹, C. Ravit², M. Jurczak¹, G. Badenes^1
1IMEC, Leuven, Belgium
²Philips Research, Leuven, Belgium

D26.2
16.50 Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits
N. Zamdmer¹, J.-O. Plouchart², J. Kim¹, L.-H. Lu², S. Narasimha¹, P. O'Neil¹, A. Ray¹, M. Sherony¹, L. Wagner^1
1IBM Microelectronics SRDC, NY, United States
²IBM T. J. Watson Research Center, United States

D26.3
17.10 New mechanism of body charging in partially depleted SOI-MOSFETs with ultra-thin gate oxides
J. Pretet^1,2, T. Matsumoto², T. Poiroux³, S. Cristoloveanu², R. Gwoziecki³, C.e Raynaud³, A. Roveda⁶, H. Brut^1
1STMicroelectronics, France
²IMEP, France
³CEA-LETI, France

D26.4
17.30 Substrate Effects on the Small-Signal Characteristics of SOI MOSFETs
V. Kilchytska¹, D. Levacq¹, D. Lederer², J.-P. Raskin², D. Flandre^1
1CeRMIN, DICE, Université Catholique de Louvain, Belgium
²CeRMIN, EMIC, Université Catholique de Louvain, Belgium

Room: Sala 4

Chairman:
Eugenio Cantatore, Philips, Eindhoven, The Netherlands

D27.1
16.30 Hybrid metal-organic photodetectors based on a new class of metal-dithiolenes
D. Natali¹, M. Sampietro¹, M. Arca², C. Denotti², F. Devillanova^2
1Politecnico di Milano, Italy
²Universitŕ degli Studi di Cagliari, Italy

D27.2
16.50 Fast polymer integrated circuits based on a polyfluorene derivative
W. Fix¹, A. Ullmann¹, J. Ficker¹, H. Rost¹, W. Clemens¹, D. Brennan², D. Welsh², J. O'Brien^2
1Siemens AG, CT MM 1, Germany, Erlangen, Germany
²The Dow Chemical Company, United States

D27.3
17.10 Novel small-dimension poly-Si TFTs with improved driving current and suppressed short channel effects
H. Wen Zan, C. Yen Chang
National Chiao Tung University, Taiwan

D27.4
17.30 An Ultra-Thin Polycrystalline-Silicon Thin-Film Transistor with SiGe Raised Source/Drain
D.-Z. Peng, P.-S. Shih, H.-W. Zan, T.-S. Liao, C.-Y. Chang
Institute of Electronics, National Chiao Tung Univ, Taiwan

Chairman:
Elena Gnani, University of Bologna, Italy

D1 Design Sensitivity in Quasi-One-Dimensional Silicon-Based Photonic Crystalline Waveguides
A. Shimizu, Y. Iida, Y. Omura
Kansai University, Suita, Japan

D2 High reproducible ideal SiC Schottky rectifiers by controlling surface preparation and thermal treatments
F. Roccaforte, F. La Via, V. Raineri
CNR-IMM, Catania, Italy

D3 Study of Hot-spot Phenomena in Cellular Power Transistors by Analytical Electro-Thermal Simulation
P. E. Bagnoli¹, S. Di Pascoli¹, G. Breglio^2
1Dip. Ingegneria dell'Informazione, Univ. di Pisa, Italy
²Dip. di Elettronica, Univ. di Napoli "Federico II", Italy

D4 The Double-Bandgap-Narrowing Transistor
A. Gruhle, H. Kibbel
DaimlerChrysler Research, Ulm, Germany

D5 Experimental study of depletion mode Si/SiGe MOSFETs for low-temperature operation
K. Fobelets¹, R. Ferguson¹, V. Gaspari¹, E. Velazquez², K. Michelakis¹, S. Despotopoulos¹, J. Zhang¹, C. Papavassiliou^1
1Imperial College of Science, London, United Kingdom
²Universidad de Salamanca, Spain

D6 Degradation Dynamics for Deep Scaled p-MOSFET's during Hot-Carrier Stress
C. Monzio Compagnoni, A. Pirovano, A. L. Lacaita
DEI, Politecnico di Milano, Italy

D7 Investigation of performance improvement and gate-to-junction leakage reduction for the 90nm CMOS gate stack architecture
K. Henson, S. Kubicek, A. Redolfi, K. De Meyer, M. Jurczak, E. Augendre
IMEC, Leuven, Belgium

D8 Effect of Pulsed Stress on Leakage Current In MOS Capacitors For Non-Volatile Memory Applications
D. Caputo¹, R. Feruglio¹, F. Irrera¹, B. Ricco'^2
1University of Rome "La Sapienza", Italy
²DEIS, University of Bologna, Italy

D9 Highly Extendible Memory Cell Architecture for Reliable Data Retention Time for 0.10mm Technology Node and beyond
J. Lee, C. Cho, J. Lee, S. Shin, J.-W. Lee, D. Kwak, K. Lee, B. Roh, T. Chung, K. Kim
Samsung Electronics Co., Yongin-City, Kyungki-Do, Korea (South)

D10 Gate Material Properties Induced 0.25µm SRAM Marginality
P. Sallagoity, O. Diop, P. Merenda, M. Juge, F. Oudin, G. Beaulieu, L. Seube, F. Gra
STMicroelectronics Rousset, France

D11 Influence of Doping Profile and Halo Implantation on the Threshold Voltage Mismatch of a 0.13um CMOS Technology
J. A. Croon^1,2, E. Augendre¹, S. Decoutere¹, W. Sansen², H. E. Maes^1,2
1IMEC, Belgium
²K.U. Leuven, Belgium

D12 Impact of ALCVD and PVD Titanium Nitride Deposition on Metal Gate Capacitors
G. Sansigolo Lujan¹, T. Schram¹, L. Pantisano¹, J. Hooker², S. Kubicek¹, E. Rohr¹, J. Schuhmacher¹, O. Kilpela³, H. Sprey³, S. De Gendt¹, K. De Meyer^1
1Imec, Leuven, Belgium
²Philips Research Leuven, Kapeldreef 75, 3001 Leuve
³ASM Process Application Development, Kapeldreef 75

D13 Stability of High-k Thin Films in Moisture Ambience - The Effect of Dissolution Gas from Acryl Apparatus
S. Akama, A. Kikuchi, J. Tonotani, S.-I Ohmi, H. Iwai
Tokyo Institute of Technology, Japan

D14 Annealing Condition Dependence of Electrical Characteristics
J. Taguchi, H. Yamamoto, J. Tonotani, S.-I. Ohmi, H. Iwai
Tokyo Institute of Technology, Japan

D15 Mechanisms of dopant redistribution and retention in Silicon following ultra-low energy Boron implantation and excimer laser annealing
L. Mariucci¹, G. Fortunato¹, S. Whelan², V. Privitera², G. Mannino^2
1CNR-IFN, Roma, Italy
²CNR-IMM, Catania, Italy

D16 Simulation of high-K tunnel barriers for nonvolatile floating gate memories
M. Specht, M. Städele, F. Hofmann
Infineon Technologies AG, Munich, Germany

D17 Optimization of Single Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliability
J. C. S. Woo¹, Neeraj K. Jha², V. Ramgopal Rao^2
1University of California, United States
²Indian Institute of Technology, Mumbai, India

D18 A New Compact Horizontal Current Bipolar Transistor (HCBT) Fabricated in (110) Wafers
T. Suligoj³, K. Wang², M. Koricic¹, P. Biljanovic^1
1Faculty of Elec Eng. and Comp., Univ. of Zagreb, Croatia
²Device Research Laboratory, UCLA, United States
³Hong Kong Universty of Science and Tech., China

D19 Effects of Boron and Germanium Base Profiles on SiGe and SiGe:C BJT Characteristics
A. Sadovnikov¹, C. Printy¹, T. Budri¹, R. Loo², P. Meunier-Beillard², M. El-Diwany^1
1National Semiconductor Corp., Santa Clara, CA, United States
²IMEC, Leuven, Belgium

D21 Microwave noise Modeling of the 0.18um Gate Length Mosfets with a 60GHz cut-off frequency
P. Sakalas¹, A. Litwin², H. Zirath³, M. Schroter^1
1Dresden University of Technology, Germany
²Ericsson Microelectronics AB, Sweden
³Chalmers University of Technology, Sweden

D22 Modeling the C-V Characteristics of Heterodimensional Schottky Contacts
R. Ragi¹, J. Manzoli¹, M. Romero¹, B. Nabet^2
1University of Sao Paulo, Sao Carlos, Brazil
²Drexel University, United States

D23 A New Test Structure for In-situ Measurements of interface Recombination During Surface Treatments
S. Daliento¹, A. Sanseverino¹, P. Spirito¹, F. Roca^2
1Diet, University of Napoli, Italy
²Enea Portici, Napoli, Italy

D24 Effects of Stress-Induced Bandgap Narrowing on Reverse-Bias Junction Behavior
V. Gopinath¹, V. Palankovski², S. Aronowitz¹, S. Selberherr^2
1LSI Logic Corporation, Santa Clara, CA, United States
²Technical University Vienna, Austria

D25 Experimental Verification of the Smoothie Database Model for Third and Fifth Order Intermodulation Distortion
V. Cuoco, M. P. van d. Heijden, M. Pelk, L. C. N. de Vreede
Technical Univerisy of Delft, The Netherlands

D26 Physics of the subthreshold slope - initial improvement and final degradation in short CMOS devices
R. Gwoziecki¹, T. Skotnicki^2
1LETI, CEA, Grenoble, France, France
²STMicroelectronics, Crolles, France

D27 Device Model of Integrated QWIP-HBT-LED Pixel for Infrared Focal Plane Arrays
V. Ryzhii¹, I. Khmyrova¹, S. Oktyabrsky^2
1University of Aizu, Aizu-Wakamatsu, Japan
²State University of New York at Albany, United States

D28 Integrated Si-based Opto-Couplers: a Novel Approach to Galvanic Isolation
A. S. Alessandria, L. La Magna, M. C. Renna, L. Fragapane, S. Coffa
STMicroelectronics Srl, Catania, Italy

D29 Electron Transit Time Enhancement In Photodetectors For High Speed Imaging
T. Kundu, R.K. Jarwal, D. Misra
ECE Dept., New Jersey, United States

D30 Photodetector with Internal Aiding Field Based-on GaAs/AlGaAs Heterostructures
A. Cola¹, F. Quaranta¹, B. Nabet², A. Cataldo^3
1CNR IMM Lecce, Italy
²ECE Dept, Drexel University, United States
³Dip. Ing. Innovazione, University of Lecce, Italy

D31 Bulk Wafer Defects Observable in Vision Chips
A. Rantzer¹, C. Svensson^2
1Integrated Vision Products AB, Linköping, Sweden
²Electronic Devices, Linköping, Sweden